TeraScale (microarchitecture)

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TeraScale is the codename for a family of graphics processing unit microarchitectures developed by ATI Technologies/AMD and their second microarchitecture implementing the unified shader model following Xenos. TeraScale replaced the old fixed-pipeline microarchitectures and competed directly with Nvidia's first unified shader microarchitecture named Tesla.^[1][2]

TeraScale was used in Radeon HD 2000 manufactured in 80 nm and 65 nm, Radeon HD 3000 manufactured in 65 nm and 55 nm, Radeon HD 4000 manufactured in 55 nm and 40 nm, Radeon HD 5000 and Radeon HD 6000 manufactured in 40 nm. TeraScale was also used in the AMD Accelerated Processing Units code-named "Brazos", "Llano", "Trinity" and "Richland". TeraScale is even found in some of the succeeding graphics cards brands.

TeraScale is a VLIW SIMD architecture, while Tesla is a RISC SIMD architecture, similar to TeraScale's successor Graphics Core Next. TeraScale implements HyperZ.^[3]

An LLVM code generator (i.e. a compiler back-end) is available for TeraScale,^[4] but it seems to be missing in LLVM's matrix.^[5] E.g. Mesa 3D makes use of it.